WSN
Low-Voltage RF Design in 45nm and Beyond
Time: Sunday, June 15th, 1pm - 5pm
Topics & Speakers:
- Radio-Frequency Receiver Design in 45nm Digital CMOS Technology - Dr. Christopher D. Hull (Intel Corp.)
- Transmitters in 45nm and Beyond : Whither Linear - Dr. Earl McCune (Panasonic)
- Challenges in Low Voltage Frequency Synthesizer Design - Prof. Sudhakar Pamarti (UCLA)
- A/D Converter Design in 45nm and Beyond - Prof. Boris Murmann (Stanford University)
Organizers:
Dr. Stewart S. Taylor (Intel Corp.)
Dr. Jacques C. Rudell (Intel Corp.)
Sponsors: RFIC
Workshop Abstract:
Architecture and circuit refinements/evolution have postponed the pain of low-voltage design. With most 45nm processes using a 1V supply, radical new thinking is required to realize high performance front-end transceivers in current and future silicon CMOS technologies. Although the intrinsic speed of the device (ft) has now reached well into the 100GHz region, new challenges with respect to low gain (gm*Ro), higher 1/f noise, extreme mismatch conditions, and low supply voltages will require a new design paradigm. This half day workshop will focus on some of the key challenges associated with realizing robust circuits in 45nm processes and beyond. The first speaker will focus on receiver architectures and circuits for nanometer technologies while the second speaker will give a similar presentation on transmitter design. The third presentation will focus on synthesizers and finally, the fourth presentation will focus on data converters. |
