WSG
Analog-Digital Co-Design Techniques for Nanometer CMOS Transceiver SoC Integration

Time: Sunday, June 15th, 1pm - 5pm

Topics & Speakers:

1. Correcting Nanometer CMOS RF Circuit Impairments – Prof. Bram Nauta (University of Twente)
   
   
2. Circuit Design Techniques for Ultra-low Voltage RF Receiver - Prof. Peter Kinget (Columbia University)
   
   
3. Analog-assisted digital and digitally-enhanced analog techniques for mixed signal SoC transceivers - Prof. John Long (University of Delft)
   
   
4. Digital signal processing techniques for linearity and efficiency enhancement of Envelope Tracking, EER, and Doherty amplifiers. Prof. Larry Larson (UC San Diego)
   
   
5. Designing CMOS wireless system-on-a-chip for WLAN - Dr. David Su (Atheros)
   
   
6. Advantages of SoC for cellular RF transceiver design - Dr. Andre Hanke (Infineon)
   

Organizers:

Dr. Bogdan Staszewski, Texas Instruments
Prof. Yann Deval, IMS, University of Bordeaux
Dr. Adrian Maxim, Siicon Laboratories

Sponsors: RFIC

Workshop Abstract:

The nanometer CMOS processes bring devices with high fT, enabling the SoC integration of multi-GHz RF communication systems. This gave a tremendous cost, area and power saving when compared with traditional bipolar or BiCMOS solutions. However, the higher noise, larger mismatches and wider process variations of nanometer FETs require extensive digital calibration to compete with traditional analog solutions. This workshop addresses advanced analog-digital codesign techniques which trade the higher speed and larger digital gate density of nanometer CMOS processes for relaxed analog front-end specifications. First, the ways to correct the nanometer CMOS device impairments and the very low-voltage circuit design challenges are presented. Then, new mixed-signal and all-digital approaches to implement traditional analog functions are investigated. Final presentations show how the analog-digital co-design techniques are applied to the major wireless applications: cellular, WLAN and broadcast.