WSE
Advanced PLL Architectures for Embedded SoC Applications
Time: Sunday, June 15th, 8am - Noon
Topics & Speakers:
- Digital Clock and Data Recovery for Software Programmable Links, Jafar Savoj, Rambus Inc
- Why Moore’s law and scaling work for mm-wave CMOS Synthesizers: Dr. Sorin Voinigescu, University of Toronto
- Understanding Digital Quantization in Delta-Sigma and Related Fractional-N PLLs, Dr. Sudhakar Pamarti, UCLA
- Digital Implementation Techniques for Fractional-N Frequency Synthesizers, Dr. Michael Perott, MIT
- All-digital PLL Architectures for Fully-integrated Receiver SoCs, Dr. Francesco Svelto, University of Pavia
Organizers:
Dr. Bertan Bakkaloglu, Arizona State University
Prof. Sayfe Kiaei, Arizona State University
Sponsors: RFIC
Workshop Abstract:
The ongoing migration of RF systems towards single-chip mixed-signal receiver/transceiver SoCs pushed towards a more digital-friendly implementation of the RF frequency synthesizers. The speed of modern CMOS technologies and advances in digital signal processing have enabled the evolution of PLL clock synthesis and clock and data recovery (CDR) circuits from analog to digital architectures. Digital solutions benefit from reduction of area and power consumption with device scaling, and facilitate porting of circuits across process nodes. Such designs achieve much lower power consumption, higher levels of integration, and improved immunity to supply and substrate noise compared to their analog counterparts. This workshop discusses state of the art approaches to digital intensive PLLs for SoC applications. |
