08:00-17:00 WSD

"Nanoscale RFIC Design Challenges and Foundry Solutions"

Topics and Speakers:

• Advanced Nanoscale RFCMOS Foundry Technology Challenges and Solutions, J. Chern, S. Liu, TSMC
  
  
• Nanoscale RFCMOS Foundry Technologies and Design Support, A. Yen, UMC
  
  
• Design Challenge of ESD Protection,RF I/O,and Low Voltage Consideration in Mixed Process Note Deep Submicron and Nanometer CMOS Technologies, P .Ouyang, T. Yu, F.Lo, I.C.Chen and L.W. Yang, SMIC, R.Huang, H. Liao, PKU, Beijing, Y. Cheng, SHRIME, Peking U., A. Wang, Illinois Institute of Technology
  
  
• Foundry Solutions for Next-Generation RFIC Design, M. Racanelli, Jazz Semiconductor
  
  
• Topics in Wireless RFIC Design Methodology Going to Submicron
  Semiconductor Processes, R. A. Mullen, Cadence Design System
  
  
• RF SiP Solution and Challenges, C. T. Chiu, ASE Corp.
  
  
• Enhancing Overall Nanoscale RF CMOS System Performance with the Right Packaging Solution, N. Karim, Amkor Technology
  
  
• CMOS Scaling Impacts to RF/Mixed-Signal Circuit Design, M.C.Frank Chang, UCLA
  
  
• CMOS RF Transceivers for 5-GHz Broadband Wireless Access, S. S. Lu, H. C. Chen, National Taiwan U.
  
  
• Mixed-Signal Design Techniques for Deep-Submicron CMOS Single-Chip Receiver SOCs, A. Maxim and R. Poorfard, Silicon Laboratories
  
  
• Device Variability of Nanoscale RF CMOS Circuits and its System Mitigation,B. Staszewski and O.Eliezer, Texas Instruments Inc.
  

Organizers: L. W. Yang, SMIC; K. C. Wang, UMC; J. Lin, University of Florida

Sponsors: RFIC, MTT-9

Semiconductor foundries have been playing an increasingly important role in IC industry. RFCMOS technologies are mostly based on the processes for digital applications.The traditional RF design techniques are limited by transistor leakage current, device mismatches, passive components, ESD protection,noise and substrate modeling. This workshop addresses these limitations and solutions.