13:00–17:00 WSC

"Optimum CMOS Integrated LNA Design Techniques for Handsets"

Topics and Speakers:

• Design of CMOS Receiver LNAs, J.Long, Delft University of Technology
  
  
• State of the Art Techniques for High Linearity Integrated CMOS Low Noise Amplifiers, V. Aparin, Qualcomm
  
  
• Modulated-Signal Distortion Measurements to Support Nonlinear Circuit Simulation, K. Remley, NIST
  
  
• Device Modeling and Technology Parameters Affecting LNA Performance, J.Pekarik, IBM
  
  
• Interface, Co-Integration and Stability Aspects of Modern CMOS LNA Designs, T. McKay, RFMD
  
  
• Case Studies of Three Cellular LNA Designs in 90nm CMOS, D. Griffith and S. Pennisi, Texas Instruments
  

Organizers: T. McKay, RFMD; J. Pekarik, IBM; L. Reynolds, RFMD

Sponsor: RFIC

This workshop will cover new techniques specific to CMOS LNA design for handsets in existing and emerging standards bands in the 800MHz to 6GHz frequency range. Focus on exploiting CMOS technology, with learning from 0.25 μm through 90 nm, emphasizing 90 nm and below where design iteration is prohibitive and excellence is demanded. By expounding on issues such as source mismatch, stability, nonlinear simulation accuracy, manufacturability, increased confidence in new techniques is developed.