08:00-17:00 TSB

"Analog and High-Speed Circuit Design Solutions for Nano RFCMOS"

Topics and Speakers:

• RFIC Case Study, D.Schmidt, Intel Corporation
  
  
• Challenges for Nanoscale Transceivers Embedded in Highly Complex SoC´s, A. Hanke, Infineon Technologies
  
  
• Digital RF Processor (DRP™) Wireless SoC in Nano RF CMOS, S. Pennisi, Texas Instruments
  
  
• Silicon – Package Co-Design, N.Karim, Amkor
  
  
• Overview of 90 nm Challenges, A.Yen, UMC Corporation
  
  
• On-chip Transformer Cascode Circuit Design Techniques, D.Huang, UCLA
  
  
• EDA Design Solutions for Nano CMOS, D. Wu, Ansoft Corporation
  
  
• Nano-scale CMOS Computer Hands-on Session, D. Wu, Ansoft Corporation

Organizer: L. I. Williams, Ansoft Corporation; Y.Cheng,
Siliconlinx Inc.

Sponsor: RFIC

Better performance and integration motivates RF designers to implement circuits at the 90-nm node and below.This scaling enables greater performance but introduces significant risks for designing and fabricating RF, analog, and high-speed circuits. This workshop provides practical design solutions to challenges of nanoscale CMOS by leading experts in IC design,packaging, foundry, and EDA. Issues such as low-threshold voltage, noise, high leakage, high variability, and DFM will be explored. A unique computer handson session allows attendees to simulate many of the concepts covered.