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2006 IEEE RFIC Symposium
Sunday workshop
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WSA:
CHALLENGES OF SYSTEMINTEGRATION IN
WIRELESS AND NANO SCALE ERA
Date & Time: Sunday, June 11; 8:00 AM to 5:00 PM
Location: Moscone Convention Center, TBD
Topics & Speakers:
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Foundry Solutions for RF SoC Design, Albert Yen, UMC
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EDA Challenges for RF SoC Design, Scott Wedge, Synopsys
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RF/Analog Mixed-Signal SoC Simulation Challenges and Solutions, Charles Gore,
Mentor Graphics
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Radios for Next Generation Wireless Networks, Reza Rofougaran, Broadcom
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Electrical Signal Integrity Analysis in Mixed-Signal and RF ICs,
François Clement, CWS
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Design Flow for Mixed Signal SoC and SiP Integration, François
Lemery, STM
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Power Performance exploration for a low rate pulsed UWB receiver, G. Gielen, KUL
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A 60 GHz Wireless SoC in CMOS, Luiz Maria Franca Neto, Intel
Organizers:
Yuhua Cheng, Siliconlinx Inc.
Didier Belot, ST Microelectronics
Jean Baptiste Begueret, IXL Laboratory
Sponsors: MTT-23: RFIC
As the semiconductor industry continually drives our life into 21st century with increased productivity and improved convenience throughout the economy, the IC industry is heavily investing in developing a technology platform for RF system integration in nano-scale and wireless era, in order to support the significantly increased demand for compact, low cost, and low power wireless products. Because both design and manufacturing technologies become much more complex in the nano-scale and RF world for RF system implementation, the challenges in designing and manufacturing chips with higher yields become much bigger than ever. These changes bring a new way of thinking in design and manufacturing. With a lot of fundamentals to be understood and a lot of technical barriers to be overcome, this workshop will bring the experts from foundries, EDA vendors and design companies to review the technology trends, challenges and opportunities in the development of an advanced platform technology for system implementation. A lot of details in advanced process technologies, device modeling, EDA design tools, design methodologies, system architecture and integration, packaging and testing will be addressed. The outcome will be greatly beneficial to the RF IC designers and technology platform developers in both industry and universities.
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(c)Copyright 2005-2006 IEEE 2006 RFIC Symposium. All rights reserved.
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| Important Dates |
| Paper Submission Due
2 Jan, 2006
Program book, conference and hotel registration open
Early March, 2006
Final Manuscript Due
6 March, 2006
RFIC 2006
11-13 June, 2006
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