WSF:
RFIC Technology Evolution and Reality
Challenges to Designers and Manufacturers
Date & Time: Sunday, June 6; 8:00 AM
to 5:00 PM
Location: Fort Worth Convention Center, Room
201A
Topics & Speakers:
- Challenges in Bridging Manufacturing and Design for RF
Applications: An Overview of Advanced Device Modeling for
RF Circuit Design,
Yuhua Cheng, Skyworks Solutions
- Challenges and Realization of RFIC in SOC,
Patrick Lin, United Microelectronics
Corp.
- Technologies for Highly Integrated RF Sub-Systems,
Paul Kempf, Jazz Semiconductor
- Opportunities and Challenges for Mixed-Signal Applications
of SiGe HBT BiCMOS Technology,
John D. Cressler, Georgia Institute
of Technology
- Various Issues on RF CMOS,
Albert Wang, Illinois Institute of
Technology
- CMOS Technology for RF/Mixed-Signal Applications –
Progresses and Challenges,
John G. J. Chern, Taiwan Semiconductor
Manufacturing Company
- Low Noise Frequency Synthesis and Clock Generation,
Marc Tiebout, Infineon
- High Speed Wireline Building Blocks,
Daniel Kehrer, Infineon
- SiGe BiCMOS, CMOS, and MEMs Processes Availability in
Order to Integrate RF Transceivers,
Didier Belot, ST Microelectronics
- Practical Aspects of a CMOS Integrated Radio,
Ken Maggio, Texas Instruments
- Software Technology for RFIC Design,
Stephen Maas, Applied Wave Research
Organizers:
Li-Wu Yang, RF Integrated Corp.
Jenshan Lin, University of Florida
Sally Liu, RF Integrated Corp.
Sponsors:
MTT-6: Microwave and Millimeter-Wave Integrated Circuits
MTT-23: RF Integrated Circuits
2004 RFIC Symposium
The growth of end-market applications that require devices
optimized for RF and high-speed electronic functions has created
demand for technologies that have been, to date, dominated
by captive suppliers. Historically high prices and significant
entrance barriers for SiGe BiCMOS have created a common view
that CMOS is the cheapest solution. This situation has also
resulted in a number of innovative CMOS architectures and
circuits for RF applications. Meanwhile, optimization of process
modules in SiGe BiCMOS is improving the performance and functional
density for RF and mixed-signal products, while enabling the
integration of functions that are beyond the reach of leading
edge CMOS. The process attributes of today’s SiGe BiCMOS
and RF CMOS technologies will be reviewed with examples of
key products on the roadmap to highly integrated RF sub-systems.
As the wireless market demands more and more designs with
RF, mixed-mode and digital integration with CMOS, the challenges
to the designers are enormous: device and noise modeling,
passive component design, IO pad design, RF ESD, package modeling,
circuit implementation, and SOC architecture. The engineering
teams at fabrication have been working to narrow the gap by
providing an easy-to-use MM/RF design tools such as P-cell,
schematic driven automatic layout, design parameter callback
function and accurate MM/RF models. The integrated design
environment and multiple EDA tools provide rapid migration
paths to advanced technologies. It shortens the product introduction
cycle.
For digital applications, the threshold and saturation current
of MOSFET are dominated by DC analysis, while for rf applications,
the Cgs and Cgd are dominated by AC analysis. In order to
overcome those challenges, IC manufacturers have developed
a methodology on high frequency device modeling. This includes
parasitic, noise, and distortion modeling. The EM design methodology
(EMDM) is used to model the passive components (L, C, Transformer)
with high accuracy. The recent development to provide a complete
design tools and environment at a manufacturer site will be
reported, followed by a successful story of a fabless company
in WLAN/PAN applications.
An overview of advanced device modeling for RF circuit design
will be presented and discussed. Since the CMOS technology
has been explored for RF IC design as a possible solution
of low cost and high integration driven by system-on-chip,
accurate and efficient RF device models are required. We will
review issues that must be properly accounted for in modeling
high frequency small signal, noise, and distortion in technologies
that can be used practically for RF applications. Challenges
and new effects in modeling devices in technologies that can
be considered as potential candidates for SOC and/or SIP applications
will be discussed to predict both the small signal and large
signal behavior. Advanced statistical modeling will also be
addressed as an effective and physical approach in design
optimization and circuit performance improvement.
The SiGe HBT technology combines transistor performance competitive
with III-V technologies with the processing maturity, integration
levels, yield, and hence cost commonly associated with conventional
Si CMOS fabrication. It has emerged from the research laboratory,
entered manufacturing on 200mm wafers, and is currently aggressively
making inroads in the high-performance communications IC market
in North America, Europe, and the Far East. A presentation
with main focus on SiGe technology provides a comprehensive
look at state-of-the-art SiGe HBTs and their suitability for
emerging mixed-signal circuit applications, including: device
operation and design, technology evolution, and performance
metrics for mixed-signal circuits and systems. We conclude
with a personal view of the opportunities and challenges for
SiGe as we look outward into the future.
First-generation (0.5µm) SiGe HBT technology is in
world-wide production, can simultaneously deliver: fT in excess
of 50 GHz, fmax in excess of 70 GHz, minimum noise figure
below 0.5 dB at 2.0 GHz, linearity efficiency (OIP3/Pdc) above
10, and 1/f noise corner frequencies below 1 kHz, all at very
low power, and thus SiGe technology offers many interesting
possibilities for mixed-signal circuits for a wide variety
of wireless and wired applications. In addition, SiGe technology
capabilities are evolving rapidly, with aggressively-scaled
SiGe HBTs capable of greater than 200-300 GHz transistor-level
performance, while achieving impressive noise performance.
The CMOS technology is gradually making inroads into some
of the RF applications, both wired line and wireless. Whether
the CMOS technology will become a major RF technology has
been a hot topic recently in the RFIC industry. Impacts of
CMOS technology advances on RF CMOS IC design will be discussed.
Various RF CMOS design issues, such as active and passive
RF devices, RF performance metrics including cut-off frequency,
power efficiency, noise figure, 1/f noises, linearity, etc
will be covered. RF CMOS block design examples will be given.
As the trend of CMOS technology scaling continues, the 90nm
technology is in production today with transistors Ft/Fmax
above 160 GHz. This makes it capable of many high frequency
applications.
This presentation will start with a comprehensive overview
on the RF CMOS technology. The progress of RF CMOS technologies
from 0.25 um, 0.18 um, 0.13 um, and up to the state-of-the-art
90 nm manufacture, including technology and device features,
will be provided. As the fact that technologies of 0.13um
and 90nm or below may not be accessible internally to most
of the designers, the role of foundry in providing such solutions
will also be discussed. A presentation in the workshop intends
to provide a convincing assessment on the outlook and challenges
of RF CMOS technology.
Modern cost driven communications systems rely on low-cost
silicon integrated circuit technologies for the front-end
receiver, transmitter and the digital signal processing functions.
The call for miniaturization, low power consumption, low cost
and the move towards higher speeds are critical trends influencing
the direction of communication system development. Todays
serial data communication systems operate at throughputs up
to 40 Gb/s.
Today the advancement of RF analog CMOS technologies has
been demonstrated to be a viable technology for very-high-bit
rate broadband and wireless communication systems up to 40
Gb/s and 40 GHz. Examples presented in the workshop will be
subtitled with two sub-session presentations; “Low Noise
Frequency Synthesis & Clock Generation” and “High
Speed Wireline Building Blocks".
Frequency synthesis or clock generation is of extreme importance
for any telecommunication or data communication system. Wireless
telecommunication systems typically use frequency synthesizers
for frequency translation and depend heavily on the phase
noise performance. Wireline data communication systems need
low jitter clocks for data detection and recovery. Mobile
systems are battery operated and need the extremely tough
combination of low noise and low power operation. The strong
demand for pure CMOS solutions is caused by the trend towards
higher integration offering digital flexibility and by the
tendency towards low cost consumer products. This presentation
starts with the design of voltage controlled oscillators.
The phase noise theories are presented and summarized into
a systematic low power low phase noise VCO design
strategy. This is illustrated through several fully integrated
CMOS VCOs for frequencies from 900 MHz up to 51 GHz aiming
at wireline and wireless applications. Next the design of
frequency dividers and prescalers in CMOS are presented. For
mobile systems low power consumption is crucial, which is
obtained through the use of dynamic CMOS flip-flops. For I/Q-generation
or higher frequencies CML-latches are the preferred solution.
For frequencies up to 50 GHz a direct injection locked oscillator
as frequency divider by two is proposed. Finally a fully integrated
fractional-N ?-S 13 GHz PLL in 0.13µm CMOS is presented,
demonstrating and summarizing all previously presented design
techniques.
In this workshop advanced circuit techniques and design methodologies
for high-speed wireline building blocks in CMOS are also presented.
Current mode logic (CML) designs offer the highest operating
speed most at all. Inductive peaking is also a powerful technique
to enhance the bandwidth of the circuits. Design aspects for
key blocks like flip-flops, frequency dividers and selector
circuits are discussed and critical challenges are identified.
The design procedures elaborated in this presentation are
suitable to achieve increased data transmission speed at lowest
power consumption, to enable integration of complex functions
on single chips and, ultimately, to reduce the costs for highly
integrated communication systems.
The different communications standards and their evolution
will be examined. The present and future potential applications
for wireless comminications will be outlined. A description
of available processes will be made, and an “Advantages/Drawbacks“
approach will be developed for each of them. The transceiver
architectures will be visited and tried fitting for each standard:
the application request, the processes and the architectures.
Finally, we will discuss the future software technology as
an important simulation tool to meet the design challenge
of advanced RFIC technologies. The design of Si-based RFICs
is considerably more complicated than that of microwave ICs
in GaAs or other III-V semiconductor technologies. RFICs typically
employ large numbers of devices and include RF, dc, and digital
functionality. Routing and parasitic extraction technologies
are essential, as are methods for characterizing distributed
elements on lossy substrates. Traditionally, time-domain analysis
has been used to analyze such circuits, because other simulation
technologies have not been able, until recently, to accommodate
such large circuits. Unfortunately, time-domain analysis has
never handled distributed elements well, so such elements
are frequently approximated in other ways, such as by lumped-element
equivalents. In this presentation, we will examine other methods
that show promise for dealing with the special problems of
designing RFICs, including the use of harmonic-balance analysis
and advanced methods for accommodating distributed elements.
We also show how advanced software technology itself is as
important as simulation technology for the design of RFICs.
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